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Riviera-PRO 2012.10

 

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ALINT 2012.01 SR1

 

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HES-7

 

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Actel RTAX and RTSX Prototyping

Specialty Solutions

DO-254 Compliance Testing

FPGA and ASIC Verification Products

Active-HDL is a Windows-based, integrated FPGA Design Creation and Simulation solution for team-based environments. Active-HDL’s Integrated Design Environment (IDE) includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for rapid deployment and verification of FPGA designs.

Riviera-PRO addresses verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.

ALINT design analysis tool decreases verification time dramatically by identifying critical issues early in the design stage. Smart design rule checking (linting) points out coding style, functional, and structural problems that are extremely difficult to debug in simulators and prevents those issues from spreading into the downstream stages of design flow.

HES-7 provides SoC/ASIC hardware verification and software validation teams with a scalable and high quality FPGA-based ASIC prototyping solution. Each HES-7 board with dual Xilinx® Virtex®-7 2000T has 4 million FPGA logic cells or up to 24 million ASIC gates of capacity, not including the DSP and memory resources.